Differential temperature sensors: Review of applications in the test and characterization of circuits, usage and design methodology

Differential temperature sensors can be placed in integrated circuits to extract a signature ofthe power dissipated by the adjacent circuit blocks built in the same silicon die. This review paper firstdiscusses the singularity that differential temperature sensors provide with respect to other sensortopologies, with circuit monitoring being their main application. The paper focuses on the monitoringof radio-frequency analog circuits. The strategies to extract the power signature of the monitoredcircuit are reviewed, and a list of application examples in the domain of test and characterizationis provided. As a practical example, we elaborate the design methodology to conceive, step bystep, a differential temperature sensor to monitor the aging degradation in a class-A linear poweramplifier working in the 2.4 GHz Industrial Scientific Medical—ISM—band. It is discussed how,for this particular application, a sensor with a temperature resolution of 0.02 K and a high dynamicrange is required. A circuit solution for this objective is proposed, as well as recommendations for thedimensions and location of the devices that form the temperature sensor. The paper concludes with adescription of a simple procedure to monitor time variability.Postprint (published version

DLL's behavioral modeling for power consumption and jitter fast optimization

This paper analyzes the sources of jitter in a DLL and presents a behavioral model for fast DLL optimization. An algorithm to simulate the DLL in open loop is demonstrated. This procedure, together with the behavioral modeling, greatly reduces the simulation time of DLL when compared to the closeloop DLL simulation. In order to optimize the DLL performance, the dependence of the output jitter versus the power consumption is studied.Postprint (author’s final draft

Providing an UWB-IR BAN wireless communications network and its application to design a low power transceiver in CMOS technology

Ultra Wide-Band (UWB) communication techniques have received increasing attention since United States Federal Communications Commission (FCC) adopted a “First Report and Order” in 2002. Unfortunately the regulations that appeared a few years latter didn't have the same level of commitment and had much tighter constraints. The FCC part. 15 power spectral density limitation is depicted. Although the word-wide common bandwidth is quite scarce (7.25 to 8.5 GHz), UWB still has its niche applications. Impulse Radio (IR) implementation of UWB systems has very interesting features such as low complexity, low power consumption, low cost, high data-rate, and the ability of coexistence with other radio systems.Peer ReviewedPostprint (published version

Output Power and Gain Monitoring in RF CMOS Class A Power Amplifiers by Thermal Imaging

© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The viability of using off-chip single-shot imaging techniques for local thermal testing in integrated Radio Frequency (RF) power amplifiers (PA’s) is analyzed. With this approach, the frequency response of the output power and power gain of a Class A RF PA is measured, also deriving information about the intrinsic operation of its transistors. To carry out this case study, the PA is heterodynally driven, and its electrical behavior is down converted into a lower frequency thermal field acquirable with an InfraRed Lock-In Thermography (IR-LIT) system. After discussing the theory, the feasibility of the proposed approach is demonstrated and assessed with thermal sensors monolithically integrated in the PA. As crucial advantages to RF-testing, this local approach is noninvasive and demands less complex instrumentation than the mainstream commercially available solutions.Peer ReviewedPostprint (author's final draft

Single-MOSFET DC thermal sensor for RF-amplifier central frequency extraction

© 2017 Elsevier B.V. A DC thermal sensor based on a single metal-oxide-semiconductor field-effect transistor (MOSFET) is proposed to extract high-frequency electrical features of embedded circuits. The MOSFET sensor is monolithically integrated with the circuit under test (CUT) and then monitors by thermal means the DC power dissipated by the CUT, which carries high-frequency electrical information. After explaining the theory behind this testing approach, the paper demonstrates the feasibility of the proposed MOSFET sensor through simulations and experiments. These are carried out using a radio-frequency (RF) power amplifier as a CUT and thermally extracting its central frequency (440 MHz). The MOSFET sensor results are assessed using an infrared camera as a reference. The main advantage of the proposed sensing method is that the impact on the integrated circuit (IC) layout area is minimum, which is crucial when testing RF-ICs. Moreover, in comparison with previous works, the cost and complexity of the required instrumentation is lower.Postprint (author's final draft

MOSFET dynamic thermal sensor for IC testing applications

This paper analyses how a single metal-oxide-semiconductor field-effect transistor (MOSFET) can be employed as a thermal sensor to measure on-chip dynamic thermal signals caused by a power-dissipating circuit under test (CUT). The measurement is subjected to two low-pass filters (LPF). The first LPF depends on the thermal properties of the heat-conduction medium (i.e. silicon) and the CUT-sensor distance, whereas the second depends on the electrical properties of the sensing circuit such as the bias current and the dimensions of the MOSFET sensor. This is evaluated along the paper through theoretical models, simulations, and experimental data resulting from a chip fabricated in 0.35 mu m CMOS technology. Finally, the proposed thermal sensor and the knowledge extracted from this paper are applied to estimate the linearity of a radio-frequency (RF) amplifier. (C) 2016 Elsevier B.V. All rights reserved.Peer ReviewedPostprint (author's final draft

MOSFET degradation dependence on input signal power in a RF power amplifier

Aging produced by RF stress is experimentally analyzed on a RF CMOS power amplifier (PA), as a function of the stress power level. The selected circuit topology allows observing individual NMOS and PMOS transistors degradations, as well as the aging effect on the circuit functionality. A direct relation between DC MOSFETs and RF PA (gain) parameters has been observed. NMOS degradation (both in mobility and Vth) is stronger than that of the PMOS. Results suggest that transistors mobility reduction is the main cause of the RF degradation in this circuit.Postprint (published version

BPF-based thermal sensor circuit for on-chip testing of RF circuits

A new sensor topology meant to extract figures of merit of radio-frequency analog integrated circuits (RF-ICs) was experimentally validated. Implemented in a standard 0.35 µm complementary metal-oxide-semiconductor (CMOS) technology, it comprised two blocks: a single metaloxide-semiconductor (MOS) transistor acting as temperature transducer, which was placed near the circuit to monitor, and an active band-pass filter amplifier. For validation purposes, the temperature sensor was integrated with a tuned radio-frequency power amplifier (420 MHz) and MOS transistors acting as controllable dissipating devices. First, using the MOS dissipating devices, the performance and limitations of the different blocks that constitute the temperature sensor were characterized. Second, by using the heterodyne technique (applying two nearby tones) to the power amplifier (PA) and connecting the sensor output voltage to a low-cost AC voltmeter, the PA’s output power and its central frequency were monitored. As a result, this topology resulted in a low-cost approach, with high linearity and sensitivity, for RF-IC testing and variability monitoring.This research was funded by Spanish AEI–Agencia Estatal de Investigación–grant number PID2019-103869RB-C33. (X.P.) has also received founds from the Spanish Ministry of Science, Innovation and Universities through Agencia Estatal de Investigación (AEI) (projects: HIPERCELLS, RTI2018-098392B-I00, and “Fiabilidad Inteligente”, PCI2020-112028).Peer ReviewedPostprint (published version

Self-calibrating closed-loop circuit for configurable constant voltage thermal anemometers

A new circuit is described which applies a configurable voltage across an RTD while the current flowing through it is measured with a current mirror. The circuit also allows working with voltages above the IC supply voltage to cope with the high power RTD dissipation normally required in thermal anemometers. The circuit is periodically calibrated to cancel the errors and amplifier offset and therefore improves measurement accuracy. Experimental measurements of the circuit fabricated using 0.35 mu m AMS technology show the functionality and improved power efficiency.Postprint (published version

A versatile CMOS transistor array IC for the statistical characterization of time-zero variability, RTN, BTI, and HCI

Statistical characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for statistical characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 x 1800 µm²